Prof. Kim`s R.P.

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  • 16 B. H. Choi, Y. S. Yu, S. H. Son, S. W. Hwang, D. Ahn, D. H. Kim, and B. G. Park "Double-dot-like charge transport through a small size silicon single electron transistor" 10th International Conference on Modulated Semiconductor Structure, pp.211, Linz, Austria, 2001-07 PDF
  • 15 D. H. Kim, K. R. Kim, S. K. Sung, B. H. Choi, S. W. Hwang, D. Ahn, J. D. Lee, B.-G. Park "Single Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Quantum Wire" 59th Annual Device Research Conference, pp. 133-134, Notre Dame, Indiana, USA, 2001-06 PDF
  • 14 S. K. Sung, J. S. Sim, D. H. Kim, J. D. Lee, B.-G. Park "Nano-scale Patterning Based on Conventional VLSI Technology and Its Application to a Si Self-Aligned Quantum Dot Memory" 2001 Silicon Nanoelectronics Workshop, pp. 20-21, Kyoto, Japan, 2001-06
  • 13 K. R. Kim, D. H. Kim, J. D. Lee, and B.-G. Park "Single Electron Transistors Based on Silicon-On-Insulator Wire Patterened by Sidewall Masking Technology and Electrically Induced Tunnel Barriers" 2001 Silicon Nanoelectronics Workshop, pp. 42-43, Kyoto, Japan, 2001-06
  • 12 K. R. Kim, D. H. Kim, J. D. Lee, and B.-G. Park "Characteristics of Silicon-On Insulator Single Electron Transistors with Electrically Induced Tunnel Barriers" The 8th Korean Conference on Semiconductors, pp. 155-156, Seoul, Korea, 2001-02
  • 11 S. K. Sung, D. H. Kim, J.-S. Sim, J. D. Lee, and B.-G. Park "Nanoscale-wire Patterning Using Side-wall and Quantum Dot Memory Device Fabrication" The 8th Korean Conference on Semiconductors, pp. 601-602, Seoul, Korea, 2001-02 PDF
  • 10 D. H. Kim, J. D. Lee, B. G. Park, B. H. Choi, and S. W. Hwang "Single electron transistors based on silicon-on-insulator quantum wire" Seoul International Symposium on Physics of Semiconductors and Applications, pp. 63-64, 2000-11
  • 9 K. R. Kim, D. H. Kim, J. D. Lee, and B.-G. Park "A study of Single Electron Logic Characterization Using a SPICE Macro-Modeling" IEEK Summer Conference 2000, pp111-114, 2000-06
  • 8 D. H. Kim, D.-H Chae, S.-K Sung, K. R. Kim, J. D Lee, and B.-G. Park "Room Temperature SETL-Oriented Dual Gate Single Electron Transistor and its Modeling" The 7th Korean Conference on Semiconductors, pp.297-298, 2000-01
  • 7 D. H. Kim, J. D. Lee, and B.-G. Park "Room Temperature Coulomb Oscillation of a Single Electron Switch with an Electrically Formed Quantum Dot and its Modeling" Int'l Conf. on Solid State Devices and Materials, pp. 234~235, Tokyo, Japan, 1999-09 PDF
  • 6 D. H. Kim, D.-H. Chae, J. D. Lee, and B.-G. Park "Room Temperature Operation of a Single Electron Switch with an Electrically Formed Quantum Dot" the 57th Device Research Conference, California, U.S.A., p. 134~135, 1999-09 PDF
  • 5 B. G. Park, D. H. Chae, D. H. Kim, and J. D. Lee, "Room Temperature Silicon Single Electron Memory and Switch" Proceedings of the 3rd Korea-China Joint Workshop on Advanced Materials, pp. 194-200, Cheju, Korea, 1999-08
  • 4 D. H. Chae, T. S. Yoon, D. H. Kim, J. Y. Kwon, K. B. Kim, J. D. Lee, and B.-G. Park "Programming Dynamics of a single Electron memory Cell with a High-Density SiGe Nanocrystal Array at Room Temperature" Device Research Conference, pp140-141, 1999-06 PDF
  • 3 D. H. Chae, T. S. Yoon, D. H. Kim, J. Y. Kwon, CC. H. Kwak, K. R. Kim, N. J. Park, H. S. Yoon, Y. J. Lee, S. J. Jeong, J. D. Lee, K. B. Kim, and B.-G. Park "Nanocrystal Memory Cell Using High-Density Si0.73Ge0.27 Quantum Dot Array" The 6th Korean Conference on Semiconductors, pp. 51-52, Seoul, Korea, 1999-02 PDF
  • 2 D. H. Kim, J. D. Lee, B.-G. Park, and H. G. Lee "Silicon Single Electron Switch with an Electrically Formed Quantum Dot" 56th Annual Device Research Conference, Charlottesville, Virginia, 1998-06 PDF
  • 1 D. H. Kim, J. D. Lee, B.-G. Park, and H. G. Lee "Single Electron Transistors with a Dual Gate Structure" The 5th Korean Conference on Semiconductors, pp.47-50, Seoul, Korea, 1998-01