Prof. Choi`s R.P.

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  • 21 M. Jang, Y. Park, M. Jun, Y. Hyun, S.‐J. Choi, and T. Zyung "The Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process" Nanoscale Research Letters, Vol. 5 pp. 1654– 1657 2010, 2010-07 PDF
  • 20 S.‐J. Choi, J.‐W. Han, D.‐I. Moon, and Y.‐K. Choi "Analysis and Evaluation of a BJT‐Based 1T‐DRAM" IEEE Electron Device Letters, Vol. 31 No. 5 pp. 393–395, 2010-05 PDF
  • 19 S. Kim, O. Yarimaga, S.‐J. Choi, and Y.‐K. Choi "Highly durable and flexible memory based on resistance switching" Solid‐State Electronics, Vol. 54 pp. 392–396, 2010-04 PDF
  • 18 S.‐J. Choi, J.‐W. Han, S. Kim, D.‐I. Moon, M. Jang, and Y.‐K. Choi "High‐Performance Polycrystalline Silicon TFT on the Structure of a Dopant‐Segregated Schottky‐Barrier Source/Drain" IEEE Electron Device Letters, Vol. 31 No. 3 pp. 228–230, 2010-03 PDF
  • 17 C.‐J. Kim, S.‐J. Choi, S.‐W. Ryu, S. Kim, J.‐J. Chang, S. H. Bae, B.‐H. Sohn, and Y.‐K. Choi "A study of the memory effects of metallic core‐metal oxide shell nanocrystals by a micelle dipping technique" Nanotechnology, Vol. 21 No. 12 pp. 125202, 2010-03 PDF
  • 16 S.‐J. Choi, J.‐W. Han, D.‐I. Moon, M. Jang, and Y.‐K. Choi "Fin Width (Wfin) Dependence of Programming Characteristics on a Dopant‐Segregated Schottky‐Barrier (DSSB) FinFET SONOS Device for a NOR‐Type Flash Memory Device" IEEE Electron Device Letters, Vol. 31 No. 1 pp. 2009–2011, 2010-01 PDF
  • 15 K.‐W. Lee, S.‐J. Choi, J.‐H. Ahn, D.‐I. Moon, T. J. Park, S. Y. Lee, and Y.‐K. Choi "An underlap field‐effect transistor for electrical detection of influenza" Applied Physics Letters, Vol. 96 No. 3 pp. 033703, 2010-01 PDF
  • 14 S.‐J. Choi, J.‐W. Han, C.‐J. Kim, S. Kim, and Y.‐K. Choi "Improvement of the Sensing Window on a Capacitorless 1T‐DRAM of a FinFET‐Based Unified RAM" IEEE Transactions on Electron Devices, Vol. 56 No. 12 pp. 3228–3231, 2009-12 PDF
  • 13 S. Kim, S.‐J. Choi, and Y.‐K. Choi "Resistive‐Memory Embedded Unified RAM (R‐URAM)" IEEE Transactions on Electron Devices, Vol. 56 No. 11 pp. 2670–2674, 2009-11 PDF
  • 12 S.‐J. Choi, J.‐W. Han, M. Jang, and Y.‐K. Choi "Analysis of Trapped Charges in Dopant‐Segregated Schottky Barrier‐Embedded FinFET SONOS Devices" IEEE Electron Device Letters, Vol. 30 No. 10 pp. 1084–1086, 2009-10 PDF
  • 11 S.‐J. Choi, J.‐W. Han, M. Jang, C.‐J. Choi, and Y.‐K. Choi "Characterization of current injection mechanism in Schottky‐barrier metal‐oxide‐semiconductor field‐effect transistors" Applied Physics Letters, Vol. 95 pp. 083502, 2009-08 PDF
  • 10 S. Kim, S.‐J. Choi, M. Jang, and Y.‐K. Choi "Investigation of the source‐side injection characteristic of a dopant‐segregated Schottky barrier metal‐oxide‐semiconductor field‐effect‐transistor" Applied Physics Letters, Vol. 95 No. 6 pp. 063508, 2009-08 PDF
  • 9 J.‐W. Han, S.‐W. Ryu, D.‐H. Kim, C.‐J. Kim, S. Kim, D.‐I. Moon, S.‐J. Choi, and Y.‐K. Choi "Fully Depleted Polysilicon TFTs for Capacitorless 1T‐DRAM" IEEE Electron Device Letters, Vol. 30 No. 7 pp. 742–744, 2009-07 PDF
  • 8 J.‐W. Han, C.‐J. Kim, S.‐J. Choi, D.‐H. Kim, D.‐I. Moon, and Y.‐K. Choi "Gate‐to‐Source/Drain Nonoverlap Device for Soft‐Program Immune Unified RAM (URAM)" IEEE Electron Device Letters, Vol. 30 No. 5 pp. 544– 546, 2009-05 PDF
  • 7 J.‐W. Han, S.‐W. Ryu, C.‐J. Kim, S.‐J. Choi, S. Kim, J.‐H. Ahn, D.‐H. Kim, K. J. Choi, B. J. Choi, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.‐K. Choi "Energy‐Band‐Engineered Unified‐RAM (URAM) Cell on Buried Si1‐yCy Substrate for Multifunctioning Flash Memory and 1T‐DRAM" IEEE Transactions on Electron Devices, Vol. 56 No. 4 pp. 641–647, 2009-04 PDF
  • 6 S.‐W. Ryu, J.‐W. Han, C.‐J. Kim, S.‐J. Choi, S. Kim, J. S. Kim, K. H. Kim, J. S. Oh, M. H. Song, G. S. Lee, Y. C. Park, J. W. Kim, and Y.‐K. Choi "Refinement of Unified Random Access Memory" IEEE Transactions on Electron Devices, Vol. 56 No. 4 pp. 601–608, 2009-04 PDF
  • 5 S.‐J. Choi, J.‐W. Han, M. Jang, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.‐K. Choi "High Injection Efficiency and Low‐Voltage Programming in a Dopant‐Segregated Schottky Barrier (DSSB) FinFET SONOS for NOR‐Type Flash Memory" IEEE Electron Device Letters, Vol. 30 No. 3 pp. 265–268, 2009-03 PDF
  • 4 J.‐W. Han, S.‐W. Ryu, S.‐J. Choi, and Y.‐K. Choi "Gate‐Induced Drain‐Leakage (GIDL) Programming Method for Soft‐Programming‐Free Operation in Unified RAM (URAM)" IEEE Electron Device Letters, Vol. 30 No. 2 pp. 189–191, 2009-02 PDF
  • 3 S.‐J. Choi, J.‐W. Han, S. Kim, M. Jang, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.‐K. Choi "Enhancement of Program Speed in Dopant‐Segregated Schottky‐Barrier (DSSB) FinFET SONOS for NAND‐Type Flash Memory" IEEE Electron Device Letters, Vol. 30 No. 1 pp. 78–81, 2009-01 PDF
  • 2 J.‐W. Han, S.‐W. Ryu, C.‐J. Kim, S. Kim, M. Im, S.‐J. Choi, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.‐K. Choi "Partially Depleted SONOS FinFET for Unified RAM (URAM)—Unified Function for High‐Speed 1T DRAM and Nonvolatile Memory" IEEE Electron Device Letters, Vol. 29 No. 7 pp. 781–783, 2008-07 PDF