Prof. Choi`s R.P.

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  • 12 M. Jang, M. Jun, Y.‐K. Choi, and S.‐J. Choi "Metal source/drain technology for nanoscale MOSFET & high speed flash applications" Semicon Korea 2010, 2010-02 PDF
  • 11 D.‐I. Moon, S.‐J. Choi, J.‐W. Han, and Y.‐K. Choi "A Study of a BJT based capacitorless 1T‐DRAM with Consideration of Geometrical Dependence" Proceedings of the 17th Korean Conference on Semiconductors, pp. 7‐8, Daegu, 2010-02 PDF
  • 10 Y.‐K. Choi, M. Jang, and S.‐J. Choi "High speed Flash Memory by a Dopant‐Segregated Schottky‐Barrier MOSFET" 2009 Bulletin of the Korean Physical Society, pp. 191, 2009-10 PDF
  • 9 S.‐J. Choi, J.‐W. Han, S. Kim, D.‐I. Moon, M. Jang, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.‐K. Choi "Performance Breakthrough in NOR Flash Memory with Dopant‐Segregated Schottky‐Barrier (DSSB) SONOS Devices" Symposium on VLSI Technology Digest of Technical Papers (VLSI), pp. 222‐223, 2009-06 PDF
  • 8 J.‐W. Han, S.‐W. Ryu, S. Kim, C.‐J. Kim, J.‐H. Ahn, S.‐J. Choi, K. J. Choi, B. J. Cho, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.‐K. Choi "Gate‐All‐Around Silicon Nanowire MOSFETs on Bulk Substrate" Proceedings of the 16th Korean Conference on Semiconductors, 2009-02 PDF
  • 7 S.‐J. Choi, S.‐W. Ryu, J.‐W. Han, S. Kim, and Y.‐K. Choi "A Novel Capacitorless DRAM Operated by Gate‐Induced Drain‐Leakage (GIDL) for Improved Sensing Window and Low Power Operation" Proceedings of the 16th Korean Conference on Semiconductors, pp. 62-63, 2009-02 PDF
  • 6 S.‐J. Choi, J.‐W. Han, S. Kim, D.‐H. Kim, M. Jang, J.‐H. Yang, J. S. Kim, K. H. Kim, J. S. Oh, M. H. Song, G. S. Lee, Y. C. Park, J. W. Kim, and Y.‐K. Choi "High Speed Flash Memory and 1T‐DRAM on Dopant Segregated Schottky Barrier (DSSB) FinFET SONOS for Multi‐functional SoC applications" IEEE International Electron Device Meeting (IEDM), 6.5, pp. 223‐226, 2008-12 PDF
  • 5 J.‐W. Han, S.‐W. Ryu, S. Kim, C.‐J. Kim, J.‐H. Ahn, S.‐J. Choi, K. J. Choi, B. J. Cho, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.‐K. Choi "Energy Band Engineered Unified‐RAM (URAM) for Multi‐Functioning 1T‐DRAM and NVM" IEEE International Electron Device Meeting (IEDM), 6.6, pp. 227‐230, 2008-12 PDF
  • 4 S.‐J. Choi, J.‐W. Han, S. Kim, C.‐J. Choi, M. Jang, and Y.‐K. Choi "Current Flow Mechanism in Schottky‐Barrier MOSFETs and Application to the 1T‐DRAM" Solid State Devices and Materials (SSDM), pp. 226‐227, 2008-09 PDF
  • 3 J.‐Woo Han, S.‐W. Ryu, S. Kim, C.‐J. Kim, J.‐H. Ahn, S.‐J. Choi, K. J. Choi, B. J. Cho, J. S. Kim, K. H. Kim, J. S. Oh, M. H. Song, G. S. Lee, Y. C. Park, J. W. Kim, and Y.‐K. Choi "Band offset FinFET‐Based URAM (Unfied‐RAM) Built on SiC for Multi‐Functioning NVM and Capacitorless DRAM" Symposium on VLSI Technology Digest of Technical Paper (VLSI), 20.3, pp. 200‐201, 2008-06 PDF
  • 2 S.‐J. Choi, J.‐W. Han, S.‐W. Ryu, S. Kim, and Y.‐K. Choi "A Comprehensive Modeling of Threshold Voltage with Consideration of Body Doping Concentration and Body Thickness in Double‐Gate FinFETs" Proceedings of the 15th Korean Conference on Semiconductors, 2008-02 PDF
  • 1 J.‐W. Han S.‐W. Ryu, S. Kim, C.‐J. Kim, M. Im, S.‐J. Choi, J. S. Kim, K. H. Kim, J. S. Oh, M. H. Song, G. S. Lee, Y. C. Park, J. W. Kim, and Y.‐K. Choi "A Unified‐RAM (URAM) Cell Multi‐Functioning Capacitorless DRAM and NVM" IEEE International Electron Device Meeting (IEDM), pp. 929‐032, 2007-12 PDF