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  • 10 S.‐J. Choi, J.‐W. Han, S. Kim, D.‐H. Kim, M. Jang, J.‐H. Yang, J. S. Kim, K. H. Kim, J. S. Oh, M. H. Song, G. S. Lee, Y. C. Park, J. W. Kim, and Y.‐K. Choi "High Speed Flash Memory and 1T‐DRAM on Dopant Segregated Schottky Barrier (DSSB) FinFET SONOS for Multi‐functional SoC applications" IEEE International Electron Device Meeting (IEDM), 6.5, pp. 223‐226, 2008-12 PDF
  • 9 J.‐W. Han, S.‐W. Ryu, S. Kim, C.‐J. Kim, J.‐H. Ahn, S.‐J. Choi, K. J. Choi, B. J. Cho, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.‐K. Choi "Energy Band Engineered Unified‐RAM (URAM) for Multi‐Functioning 1T‐DRAM and NVM" IEEE International Electron Device Meeting (IEDM), 6.6, pp. 227‐230, 2008-12 PDF
  • 8 S.‐J. Choi, J.‐W. Han, S. Kim, C.‐J. Choi, M. Jang, and Y.‐K. Choi "Current Flow Mechanism in Schottky‐Barrier MOSFETs and Application to the 1T‐DRAM" Solid State Devices and Materials (SSDM), pp. 226‐227, 2008-09 PDF
  • 7 J.‐Woo Han, S.‐W. Ryu, S. Kim, C.‐J. Kim, J.‐H. Ahn, S.‐J. Choi, K. J. Choi, B. J. Cho, J. S. Kim, K. H. Kim, J. S. Oh, M. H. Song, G. S. Lee, Y. C. Park, J. W. Kim, and Y.‐K. Choi "Band offset FinFET‐Based URAM (Unfied‐RAM) Built on SiC for Multi‐Functioning NVM and Capacitorless DRAM" Symposium on VLSI Technology Digest of Technical Paper (VLSI), 20.3, pp. 200‐201, 2008-06 PDF
  • 6 S.‐J. Choi, J.‐W. Han, S.‐W. Ryu, S. Kim, and Y.‐K. Choi "A Comprehensive Modeling of Threshold Voltage with Consideration of Body Doping Concentration and Body Thickness in Double‐Gate FinFETs" Proceedings of the 15th Korean Conference on Semiconductors, 2008-02 PDF
  • 5 K. S. Roh, G.-C. Kang, S. H. Seo, K. Y. Kim, K.-J. Song, J.-H. Park, S. Lee, C. M. Choi, K. Jeon, S. R. Park, J. Lee, T. Y. Kim, D. H. Kim , and D. M. Kim "Comparative Study on Circuit Performance Depending on Double-Gate (DG) and Triple-Gate (TG) FinFET Structure" The 15th Korean Conference on Semiconductors, 2008-02 PDF
  • 4 S. R. Park, K. Y. Kim, J.-H. Park, S. H. Seo, G.-C. Kang, K. S. Roh, S. Lee, C. M. Choi, K.-J. Song, K. Jeon, J. Lee, T. Y. Kim, D. M. Kim, and D. H. Kim "Comparative Study on Program/Erase Efficiency of 3-D SONOS Flash Memory Cell Transistor: Structural Approach from Double-Gate (DG) to Gate-All-Around (GAA) FET" The 15th Korean Conference on Semiconductors, 2008-02 PDF
  • 3 C. M. Choi, G.-C. Kang, K.-S. Roh, S.-H. Seo, K.-Y. Kim, K.-J. Song, S.-R. Park, J.-H. Park, K. Jeon, J. Lee, T. Y. Kim, D. M. Kim, and D. H. Kim "Low Power/High Speed Compact ADCs based on SET(Single-Electron Transistor)/CMOS Hybrid Circuits" The 15th Korean Conference on Semiconductors, 2008-02 PDF
  • 2 K. Jeon, S. Lee, S. H. Seo, K. S. Roh, G.-C. Kang, K. Y. Kim, C. M. Choi, K.-J. Song, S. R. Park, J.-H. Park, J. Lee, T. Y. Kim, D. H. Kim , and D. M. Kim "Optical Charge Pumping Method for Extracting the Energy Level of Interface States in Program/Erase Cycled SONOS Flash Memory Cell and Its Program Time Dependence" The 15th Korean Conference on Semiconductors, 2008-02 PDF
  • 1 K. S. Roh, G.-C. Kang, S. H. Seo, K. Y. Kim, K.-J. Song, J.-H. Park, S. Lee, C. M. Choi, K. Jeon, S. R. Park, J. Lee, T. Y. Kim, D. H. Kim , and D. M. Kim "Novel Flat Band Voltage Extraction using Optical Substrate Current and Lateral Profiling of Trapped Charges in Localized Charge Trapping Flash Memory Cells" The 15th Korean Conference on Semiconductors, 2008-02 PDF
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