28K.-W. Song, S. H. Lee, D. H. Kim, K. R. Kim, J. Kyung, G. Baek, C.-A. Lee, J. D. Lee, and B.-G. Park"Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic"33rd International Symposium on Multiple-Valued Logic, Tokyo, Japan, pp.267-272, 2003-05
27S.-H. Lee, K.-W. Song, D. H. Kim, K. R. Kim, J. D. Lee, B.-G. Park, Y.-J. Gu, G.-Y. Yang, Y.-K. Park, and J.-T. Kong"A SPICE Model of Realistic Single-Electron Transistors and its Application to Multiple-Valued Logic"The 10th Korean Conference on Semiconductors, Seoul, Korea, pp. 109-110, 2003-02
26D. H. Kim, S.-K Sung, K. R. Kim, J. D. Lee, and B.-G. Park"Single-Electron Transisters Based on Gate-Induced Si Island for Single-Electron Logic Application"IEEE 2002 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 57-58, 2002-06
25K. R. Kim, D. H. Kim, J. D. Lee, and B.-G. Park"Room Temperature Negative Differential Conductance Characteristics in 30-nm Square Channel Silicon-On-Insulator n-MOSFETs"IEEE 2002 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 9-10, 2002-06
24S. H. Lee, D. H. Kim, K.-R. Kim, J. D. Lee, and B.-G. Park"A Practival SPICE Model Based on Realistic Single-Electron Transistor"IEEE 2002 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 77-78, 2002-06
23J. S. Sim, S. K. Sung, D.-H. Chae, D. H. Kim, J. D. Lee, and B.-G. Park"Programming Characteristics of Single Quantum Dot and Nanocrystal Memories"IEEE 2002 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 65-66, 2002-06
22D. H. Kim, S.-K Sung, K. R. Kim, J. D. Lee, and B.-G. Park"Single-Electron Transistors with Sidewall Depletion Gates on an SOI Nanowire and Their Application to Single-Electron Inverter"The 9th Korean Conference on Semiconductors, Chunan, Korea, pp. 91-92, 2002-02
21D. H. Kim, S.-K. Sung, K. R. Kim, B. H. Choi, S. W. Hwang, D. Ahn, J. D. Lee, and B.-G. Park"Si Single-Electron Transistors with Sidewall Depletion Gates and their Application to Dynamic Single-Electron Transistor Logic"International Electron Devices Meeting, Washington DC, U.S.A., pp. 151-154, 2001-12
20B. H. Choi, S. H. Son, K. H. Cho, S. W. Hwang, D. Ahn, D. H. Kim, B. G. Park"Direct observation of excited states in double quantum dot silicon single electron transistor"Fifth International Symposium on New Phenomena in Mesoscopic Structures, p. 36, Big Island, Hawaii, U.S.A., 2001-11
19S. K. Sung, J. S. Sim, D. H. Kim, J. D. Lee, and B.-G. Park"Single Electron Memory with a Defined Poly-Si Dot Based on Conventioanl VLSI Technology"Int'l Conf. on Solid State Devices and Materials 2001, pp.432-433, Tokyo, Japan, 2001-09
18K. R. Kim, D. H. Kim, S. K. Sung, J. D. Lee, B.-G. Park, B. H. Choi, S. W. Hwang, and D. Ahn"Single Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Nano-Wire"Int'l Conf. on Solid State Devices and Materials 2001, pp.552-553, Tokyo, Japan, 2001-09
17B. H. Choi, Y. S. Yu, S. H. Son, S. W. Hwang, D. Ahn, D. H. Kim and B.-G. Park"Double-dot like charge transport in silicon single electron transistor"14th International Conference on the Electronic Properties of 2-dimensional System, part 2, pp.1101~1102, Pragh, Czech, 2001-08
16B. H. Choi, Y. S. Yu, S. H. Son, S. W. Hwang, D. Ahn, D. H. Kim, and B. G. Park"Double-dot-like charge transport through a small size silicon single electron transistor"10th International Conference on Modulated Semiconductor Structure, pp.211, Linz, Austria, 2001-07
15D. H. Kim, K. R. Kim, S. K. Sung, B. H. Choi, S. W. Hwang, D. Ahn, J. D. Lee, B.-G. Park"Single Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Quantum Wire"59th Annual Device Research Conference, pp. 133-134, Notre Dame, Indiana, USA, 2001-06
14S. K. Sung, J. S. Sim, D. H. Kim, J. D. Lee, B.-G. Park"Nano-scale Patterning Based on Conventional VLSI Technology and Its Application to a Si Self-Aligned Quantum Dot Memory"2001 Silicon Nanoelectronics Workshop, pp. 20-21, Kyoto, Japan, 2001-06
13K. R. Kim, D. H. Kim, J. D. Lee, and B.-G. Park"Single Electron Transistors Based on Silicon-On-Insulator Wire Patterened by Sidewall Masking Technology and Electrically Induced Tunnel Barriers"2001 Silicon Nanoelectronics Workshop, pp. 42-43, Kyoto, Japan, 2001-06
12K. R. Kim, D. H. Kim, J. D. Lee, and B.-G. Park"Characteristics of Silicon-On Insulator Single Electron Transistors with Electrically Induced Tunnel Barriers"The 8th Korean Conference on Semiconductors, pp. 155-156, Seoul, Korea, 2001-02
11S. K. Sung, D. H. Kim, J.-S. Sim, J. D. Lee, and B.-G. Park"Nanoscale-wire Patterning Using Side-wall and Quantum Dot Memory Device Fabrication"The 8th Korean Conference on Semiconductors, pp. 601-602, Seoul, Korea, 2001-02
10D. H. Kim, J. D. Lee, B. G. Park, B. H. Choi, and S. W. Hwang"Single electron transistors based on silicon-on-insulator quantum wire"Seoul International Symposium on Physics of Semiconductors and Applications, pp. 63-64, 2000-11
9K. R. Kim, D. H. Kim, J. D. Lee, and B.-G. Park"A study of Single Electron Logic Characterization Using a SPICE Macro-Modeling"IEEK Summer Conference 2000, pp111-114, 2000-06